HD64F2638F20J Datasheet, PDF (513/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 13 Serial Communication Interface (SCI)
13.2.8 Bit Rate Register (BRR)
Bit
:
7
6
5
4
3
2
1
0
Initial value :
1
1
1
1
1
1
1
1
R/W
:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BRR is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate
generator operating clock selected by bits CKS1 and CKS0 in SMR.
BRR can be read or written to by the CPU at all times.
BRR is initialized to H'FF by a reset and in standby mode.
As baud rate generator control is performed independently for each channel, different values can
be set for each channel.
Table 13-3 shows sample BRR settings in asynchronous mode, and table 13-4 shows sample BRR
settings in clocked synchronous mode.
Table 13-3 BRR Settings for Various Bit Rates (Asynchronous Mode)
Bit Rate
(bit/s)
110
150
300
600
1200
2400
4800
9600
19200
31250
38400
φ = 4 MHz
φ = 4.9152 MHz
Error
Error
n
N
(%) n
N
(%) n
2
70 0.03 2
1
207 0.16 1
1
103 0.16 1
0
207 0.16 0
0
103 0.16 0
0
51 0.16 0
0
25 0.16 0
0
12 0.16 0
———0
0
3
0.00 0
———0
86 0.31 2
255 0.00 2
127 0.00 1
255 0.00 1
127 0.00 0
63 0.00 0
31 0.00 0
15 0.00 0
7
0.00 0
4
–1.70 0
3
0.00 0
φ = 5 MHz
Error
N
(%)
88 –0.25
64 0.16
129 0.16
64 0.16
129 0.16
64 0.16
32 –1.36
15 1.73
7
1.73
4
0.00
3
1.73
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 463 of 1458