HD64F2638F20J Datasheet, PDF (608/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 15 I²C Bus Interface [Option]
(Only for the H8S/2638, H8S/2639, and H8S/2630)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Bits 2 to 0—Bit Counter (BC2 to BC0): Bits BC2 to BC0 specify the number of bits to be
transferred next. With the I²C bus format (when the FS bit in SAR or the FSX bit in SARX is 0),
the data is transferred with one addition acknowledge bit. Bit BC2 to BC0 settings should be made
during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than 000,
the setting should be made while the SCL line is low.
The bit counter is initialized to 000 by a reset and when a start condition is detected. The value
returns to 000 at the end of a data transfer, including the acknowledge bit.
Bit 2
BC2
0
1
Bit 1
BC1
0
1
0
1
Bit 0
BC0
0
1
0
1
0
1
0
1
Bits/Frame
Synchronous Serial Format I²C Bus Format
8
9
(Initial value)
1
2
2
3
3
4
4
5
5
6
6
7
7
8
Page 558 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010