HD64F2638F20J Datasheet, PDF (632/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 15 I²C Bus Interface [Option]
(Only for the H8S/2638, H8S/2639, and H8S/2630)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
SCL
(Master output)
89
SDA
(Master output)
Bit 0
Data 1 ^[7]
SDA
(Slave output)
A
ICDRE
IRIC
IRTR
ICDR
Data 1
1 234 5 67 89
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Data 2
[10]
A
Data 2
Generate start
condition
User processing
[9] ICDR write
[9] IRIC clearance
[11] ACKB read
[12] Write BBSY = 0
and SCP = 0
(generate stop
[12] IRIC clearance condition)
Figure 15-9 Example of Master Transmit Mode Stop Condition Generation Timing
(MLS = WAIT = 0)
15.3.4 Master Receive Operation
In I²C bus format master receive mode, the master device outputs the receive clock, receives data,
and returns an acknowledge signal. The slave device transmits data.
The master device transmits the data containing the slave address + R/W (0: read) in the 1st frame
after a start condition is generated in the master transmit mode. After the slave device is selected
the switch to receive operation takes place.
(1) Receive Operation Using Wait States
Figures 15-10 and 15-11 are flowcharts showing examples of the master receive mode (WAIT =
1).
Page 582 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010