HD64F2638F20J Datasheet, PDF (31/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

4.2.3 Interrupts after Reset............................................................................................ 98
4.2.4 State of On-Chip Supporting Modules after Reset Release ................................. 99
4.3 Traces................................................................................................................................ 99
4.4 Interrupts ........................................................................................................................... 100
4.5 Trap Instruction................................................................................................................. 101
4.6 Stack Status after Exception Handling.............................................................................. 102
4.7 Notes on Use of the Stack ................................................................................................. 103
Section 5 Interrupt Controller .......................................................................................... 105
5.1 Overview........................................................................................................................... 105
5.1.1 Features................................................................................................................ 105
5.1.2 Block Diagram..................................................................................................... 106
5.1.3 Pin Configuration................................................................................................. 107
5.1.4 Register Configuration......................................................................................... 107
5.2 Register Descriptions ........................................................................................................ 108
5.2.1 System Control Register (SYSCR) ...................................................................... 108
5.2.2 Interrupt Priority Registers A to H, J to M (IPRA to IPRH, IPRJ to IPRM) ....... 109
5.2.3 IRQ Enable Register (IER) .................................................................................. 110
5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 111
5.2.5 IRQ Status Register (ISR).................................................................................... 112
5.3 Interrupt Sources ............................................................................................................... 114
5.3.1 External Interrupts ............................................................................................... 114
5.3.2 Internal Interrupts ................................................................................................ 116
5.3.3 Interrupt Exception Handling Vector Table......................................................... 116
5.4 Interrupt Operation............................................................................................................ 120
5.4.1 Interrupt Control Modes and Interrupt Operation ................................................ 120
5.4.2 Interrupt Control Mode 0 ..................................................................................... 124
5.4.3 Interrupt Control Mode 2 ..................................................................................... 126
5.4.4 Interrupt Exception Handling Sequence .............................................................. 128
5.4.5 Interrupt Response Times .................................................................................... 129
5.5 Usage Notes ...................................................................................................................... 130
5.5.1 Contention between Interrupt Generation and Disabling..................................... 130
5.5.2 Instructions that Disable Interrupts ...................................................................... 131
5.5.3 Times when Interrupts Are Disabled ................................................................... 131
5.5.4 Interrupts during Execution of EEPMOV Instruction.......................................... 132
5.5.5 IRQ Interrupts ...................................................................................................... 132
5.5.6 Notes on Use of NMI Interrupt ............................................................................ 132
5.6 DTC Activation by Interrupt............................................................................................. 133
5.6.1 Overview.............................................................................................................. 133
5.6.2 Block Diagram..................................................................................................... 133
REJ09B0103-0800 Rev. 8.00
May 28, 2010
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