HD64F2638F20J Datasheet, PDF (193/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Bit 4
MSTPC4
0
1
Description
PC break controller module stop mode is cleared
PC break controller module stop mode is set
Section 6 PC Break Controller (PBC)
(Initial value)
6.3 Operation
The operation flow from break condition setting to PC break interrupt exception handling is shown
in section 6.3.1, PC Break Interrupt Due to Instruction Fetch, and 6.3.2, PC Break Interrupt Due to
Data Access, taking the example of channel A.
6.3.1 PC Break Interrupt Due to Instruction Fetch
(1) Initial settings
⎯ Set the break address in BARA. For a PC break caused by an instruction fetch, set the
address of the first instruction byte as the break address.
⎯ Set the break conditions in BCRA.
BCRA bit 6 (CDA): With a PC break caused by an instruction fetch, the bus master must
be the CPU. Set 0 to select the CPU.
BCRA bits 5 to 3 (BAMA2 to BAMA0): Set the address bits to be masked.
BCRA bits 2, 1 (CSELA1, CSELA0): Set 00 to specify an instruction fetch as the break
condition.
BCRA bit 0 (BIEA): Set to 1 to enable break interrupts.
(2) Satisfaction of break condition
⎯ When the instruction at the set address is fetched, a PC break request is generated
immediately before execution of the fetched instruction, and the condition match flag
(CMFA) is set.
(3) Interrupt handling
⎯ After priority determination by the interrupt controller, PC break interrupt exception
handling is started.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 143 of 1458