HD64F2638F20J Datasheet, PDF (689/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 16 Controller Area Network (HCAN)
Bit 9—Receive Message Interrupt Mask (IMR1): Enables or disables message reception
interrupt requests.
Bit 9: IMR1
0
1
Description
Message reception interrupt request (RM1) to CPU by IRR1 enabled
Message reception interrupt request (RM1) to CPU by IRR1 disabled
(Initial value)
Bit 8—Reserved: The reset flag cannot be masked. This bit always reads 0. The write value
should always be 0.
Bits 7 to 5, 3, and 2—Reserved: These bits always read 1. The write value should always be 1.
Bit 4—Bus Operation Interrupt Mask (IMR12): Enables or disables interrupt requests due to
bus operation in sleep mode.
Bit 4: IMR12
0
1
Description
Bus operation interrupt request (OVR0) to CPU by IRR12 enabled
Bus operation interrupt request (OVR0) to CPU by IRR12 disabled
(Initial value)
Bit 1—Unread Interrupt Mask (IMR9): Enables or disables unread receive message overwrite
interrupt requests.
Bit 1: IMR9
0
1
Description
Unread message overwrite interrupt request (OVR0) to CPU by IRR9
enabled
Unread message overwrite interrupt request (OVR0) to CPU by IRR9
disabled
(Initial value)
Bit 0—Mailbox Empty Interrupt Mask (IMR8): Enables or disables mailbox empty interrupt
requests.
Bit 0: IMR8
0
1
Description
Mailbox empty interrupt request (SLE0) to CPU by IRR8 enabled
Mailbox empty interrupt request (SLE0) to CPU by IRR8 disabled
(Initial value)
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 639 of 1458