HD64F2638F20J Datasheet, PDF (521/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 13 Serial Communication Interface (SCI)
Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. The SINV
bit does not affect the logic level of the parity bit(s): parity bit inversion requires inversion of the
O/E bit in SMR.
Bit 2
SINV
0
1
Description
TDR contents are transmitted without modification
Receive data is stored in RDR without modification
TDR contents are inverted before being transmitted
Receive data is stored in RDR in inverted form
(Initial value)
Bit 1—Reserved: This bit is always read as 1 and cannot be modified.
Bit 0—Smart Card Interface Mode Select (SMIF): When the smart card interface operates as a
normal SCI, 0 should be written in this bit.
Bit 0
SMIF
0
1
Description
Operates as normal SCI (smart card interface function disabled)
Smart card interface function enabled
(Initial value)
13.2.10 Module Stop Control Register B (MSTPCRB)
MSTPCRB
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MSTPCRB is 8-bit readable/writable registers that perform module stop mode control.
Setting any of bits MSTPB7 to MSTBP5 to 1 stops SCI0 to SCI2 operating and enter module stop
mode on completion of the bus cycle. For details, see section 23A.5, 23B.5, Module Stop Mode.
MSTPCRB is initialized to H'FF by a reset and in hardware standby mode. They are not initialized
by a manual reset and in software standby mode.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 471 of 1458