HD64F2638F20J Datasheet, PDF (151/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 4 Exception Handling
4.5 Trap Instruction
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state.
The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector
number from 0 to 3, as specified in the instruction code.
Table 4-4 shows the status of CCR and EXR after execution of trap instruction exception
handling.
Table 4-4 Status of CCR and EXR after Trap Instruction Exception Handling
Interrupt Control Mode
0
2
Legend:
1: Set to 1
0: Cleared to 0
—: Retains value prior to execution.
CCR
I
UI
1
—
1
—
EXR
I2 to I0
T
—
—
—
0
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 101 of 1458