HD64F2638F20J Datasheet, PDF (1367/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Appendix B Internal I/O Register
MSTPCRC—Module Stop Control Register C
H'FDEA
System
Bit
7
6
5
4
3
2
1
0
MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0
Initial value
1
1
1
1
1
1
1
1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Module Stop
0 Module stop mode is cleared
1 Module stop mode is set
PFCR—Pin Function Control Register
H'FDEB
System
Bit
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
AE3
AE2
AE1 AE0
Initial value
0
0
0
0
1/0
1/0
1
1/0
Read/Write
⎯
⎯
⎯
⎯
R/W
R/W
R/W
R/W
Address Output Enable 3 to 0
0 0 0 0 A8 to A23 address output disabled (Initial value*)
1 A8 address output enabled; A9 to A23 address output disabled
1 0 A8, A9 address output enabled; A10 to A23 address output disabled
1 A8 to A10 address output enabled; A11 to A23 address output disabled
1 0 0 A8 to A11 address output enabled; A12 to A23 address output disabled
1 A8 to A12 address output enabled; A13 to A23 address output disabled
1 0 A8 to A13 address output enabled; A14 to A23 address output disabled
1 A8 to A14 address output enabled; A15 to A23 address output disabled
1 0 0 0 A8 to A15 address output enabled; A16 to A23 address output disabled
1 A8 to A16 address output enabled; A17 to A23 address output disabled
1 0 A8 to A17 address output enabled; A18 to A23 address output disabled
1 A8 to A18 address output enabled; A19 to A23 address output disabled
1 0 0 A8 to A19 address output enabled; A20 to A23 address output disabled
1 A8 to A20 address output enabled; A21 to A23 address output disabled (Initial value*)
1 0 A8 to A21 address output enabled; A22, A23 address output disabled
1 A8 to A23 address output enabled
Note: * In on-chip ROM-enabled expansion mode, bits AE3 to AE0 are initialized to B'0000.
In on-chip ROM-disabled expansion mode, bits AE3 to AE0 are initialized to B'1101.
Address pins A0 to A7 are made address outputs by setting the corresponding DDR bits to 1.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 1317 of 1458