HD64F2638F20J Datasheet, PDF (864/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 21B ROM
(H8S/2638 Group, H8S/2639 Group, H8S/2630 Group)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Table 21B-7 Flash Memory Erase Blocks
Block (Size)
Addresses
EB0 (4 kbytes)
H'000000 to H'000FFF
EB1 (4 kbytes)
H'001000 to H'001FFF
EB2 (4 kbytes)
H'002000 to H'002FFF
EB3 (4 kbytes)
H'003000 to H'003FFF
EB4 (4 kbytes)
H'004000 to H'004FFF
EB5 (4 kbytes)
H'005000 to H'005FFF
EB6 (4 kbytes)
H'006000 to H'006FFF
EB7 (4 kbytes)
H'007000 to H'007FFF
EB8 (32 kbytes)
H'008000 to H'00FFFF
EB9 (64 kbytes)
H'010000 to H'01FFFF
EB10 (64 kbytes)
H'020000 to H'02FFFF
EB11 (64 kbytes)
EB12 (64 kbytes)^*
EB13 (64 kbytes))^*
H'030000 to H'03FFFF
H'040000 to H'04FFFF
H'050000 to H'05FFFF
Note: * This function is not available in the H8S/2638 and H8S/2639.
21B.7.5 RAM Emulation Register (RAMER)
RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating
real-time flash memory programming. RAMER initialized to H'00 by a reset and in hardware
standby mode. It is not initialized in software standby mode. RAMER settings should be made in
user mode or user program mode.
Flash memory area divisions are shown in table 21B-8. To ensure correct operation of the
emulation function, the ROM for which RAM emulation is performed should not be accessed
immediately after this register has been modified. Normal execution of an access immediately
after register modification is not guaranteed.
Bit: 7
—
Initial value: 0
R/W: R
6
5
4
3
2
1
0
—
—
— RAMS RAM2 RAM1 RAM0
0
0
0
0
0
0
0
R
R/W R/W R/W R/W R/W R/W
Page 814 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010