HD64F2638F20J Datasheet, PDF (1109/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Appendix A Instruction Set
Appendix A Instruction Set
A.1 Instruction List
Operand Notation
Rd
General register (destination)^*
Rs
General register (source)^*
Rn
General register^*
ERn
General register (32-bit register)
MAC
Multiply-and-accumulate register (32-bit register)
(EAd)
Destination operand
(EAs)
Source operand
EXR
Extended control register
CCR
Condition-code register
N
N (negative) flag in CCR
Z
Z (zero) flag in CCR
V
V (overflow) flag in CCR
C
C (carry) flag in CCR
PC
Program counter
SP
Stack pointer
#IMM
Immediate data
disp
Displacement
+
Add
–
Subtract
×
Multiply
÷
Divide
∧
Logical AND
∨
Logical OR
⊕
Logical exclusive OR
→
Transfer from the operand on the left to the operand on the right, or
transition from the state on the left to the state on the right
¬
Logical NOT (logical complement)
( ) <>
Contents of operand
:8/:16/:24/:32
8-, 16-, 24-, or 32-bit length
Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to
R7, E0 to E7), and 32-bit registers (ER0 to ER7).
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 1059 of 1458