HD64F2638F20J Datasheet, PDF (602/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 15 I²C Bus Interface [Option]
(Only for the H8S/2638, H8S/2639, and H8S/2630)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
TDRE
0
1
Description
The next transmit data is in ICDR (ICDRT), or transmission cannot
be started
[Clearing conditions]
(Initial value)
• When transmit data is written in ICDR (ICDRT) in transmit mode (TRS = 1)
• When a stop condition is detected in the bus line state after a stop condition is
issued with the I²C bus format or serial format selected
• When a stop condition is detected with the I²C bus format selected
• In receive mode (TRS = 0)
(A 0 write to TRS during transfer is valid after reception of a frame containing an
acknowledge bit)
The next transmit data can be written in ICDR (ICDRT)
[Setting conditions]
• In transmit mode (TRS = 1), when a start condition is detected in the bus line state
after a start condition is issued in master mode with the I²C bus format or serial
format selected
• When data is transferred from ICDRT to ICDRS
(Data transfer from ICDRT to ICDRS when TRS = 1 and TDRE = 0, and ICDRS is
empty)
• In receive mode (TRS = 0), when a switch is made from slave receive mode (TRS
= 0) to transmit mode (TRS = 1) after detection of a start condition (first time only)
RDRF
0
1
Description
The data in ICDR (ICDRR) is invalid
[Clearing condition]
(Initial value)
• When ICDR (ICDRR) receive data is read in receive mode
The ICDR (ICDRR) receive data can be read
[Setting condition]
• When data is transferred from ICDRS to ICDRR
(Data transfer from ICDRS to ICDRR in case of normal termination with TRS = 0
and RDRF = 0)
Page 552 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010