HD64F2638F20J Datasheet, PDF (764/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 19 Motor Control PWM Timer
19.1.2 Block Diagram
Figure 19-1 shows a block diagram of PWM channel 1.
Interrupt
request
Internal
data bus
φ, φ/2, φ/4, φ/8, φ/16
PWCR1
PWCNT1
Compare
match
PWCYR1
12 9
0 12 9
0
PWBFR1A
PWDTR1A
PWBFR1C
PWDTR1C
PWBFR1E
PWDTR1E
PWBFR1G
PWDTR1G
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
PWOCR1
PWPR1
P/N
P/N
P/N
P/N
P/N
P/N
P/N
P/N
Port
control
PWM1A
PWM1B
PWM1C
PWM1D
PWM1E
PWM1F
PWM1G
PWM1H
Legend:
PWCR1:
PWM control register 1
PWOCR1:
PWM output control register 1
PWPR1:
PWM polarity register 1
PWCNT1:
PWM counter 1
PWCYR1:
PWM cycle register 1
PWDTR1A, 1C, 1E, 1G: PWM duty registers 1A, 1C, 1E, 1G
PWBFR1A, 1C, 1E, 1G: PWM buffer registers 1A, 1C, 1E, 1G
Figure 19-1 Block Diagram of PWM Channel 1
Page 714 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010