HD64F2638F20J Datasheet, PDF (492/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 12 Watchdog Timer
φ
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
TCNT
Overflow signal
(internal signal)
H'FF
H'00
OVF
Figure 12-6 Timing of Setting of OVF
12.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF)
In the WDT0, the WOVF flag is set to 1 if TCNT overflows during watchdog timer operation. If
TCNT overflows while the RSTE bit in RSTCSR is set to 1, an internal reset signal is generated
for the entire chip. Figure 12-7 shows the timing in this case.
φ
TCNT
Overflow signal
(internal signal)
WOVF
Internal reset
signal
H'FF
H'00
518 states (WDT0)
515/516 states (WDT1)
Figure 12-7 Timing of Setting of WOVF
Page 442 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010