HD64F2638F20J Datasheet, PDF (441/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 10 16-Bit Timer Pulse Unit (TPU)
Contention between TGR Write and Compare Match: If a compare match occurs in the T₂
state of a TGR write cycle, the TGR write takes precedence and the compare match signal is
inhibited. A compare match does not occur even if the same value as before is written.
Figure 10-51 shows the timing in this case.
TGR write cycle
T₁
T₂
φ
Address
TGR address
Write signal
Compare
match signal
TCNT
Prohibited
N
N+1
TGR
N
M
TGR write data
Figure 10-51 Contention between TGR Write and Compare Match
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 391 of 1458