HD64F2638F20J Datasheet, PDF (1372/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Appendix B Internal I/O Register
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
IER—IRQ Enable Register
Bit
7
6
⎯
⎯
Initial value
0
0
Read/Write R/W R/W
H'FE14
Interrupt Controller
5
IRQ5E
0
R/W
4
IRQ4E
0
R/W
3
IRQ3E
0
R/W
2
IRQ2E
0
R/W
1
IRQ1E
0
R/W
0
IRQ0E
0
R/W
IRQ5 to IRQ0 Enable
0 IRQn interrupts disabled
1 IRQn interrupts enabled
(n = 5 to 0)
ISR—IRQ Status Register
H'FE15
Interrupt Controller
Bit
Initial value
Read/Write
7
⎯
0
R/(W)*
6
⎯
0
R/(W)*
5
IRQ5F
0
R/(W)*
4
IRQ4F
0
R/(W)*
3
IRQ3F
0
R/(W)*
2
IRQ2F
0
R/(W)*
1
IRQ1F
0
R/(W)*
0
IRQ0F
0
R/(W)*
IRQ5 to IRQ0 Flags
0 [Clearing conditions]
• Cleared by reading IRQnF when set to 1, then writing 0 in IRQnF
• When interrupt exception handling is executed while low-level detection
is set (IRQnSCB = IRQnSCA = 0) and IRQn input is high
• When IRQn interrupt exception handling is executed while falling, rising,
or both-edge detection is set (IRQnSCB = 1 or IRQnSCA = 1)
• When the DTC is activated by an IRQn interrupt, and the DISEL bit in
MRB of the DTC is cleared to 0
1 [Setting conditions]
• When IRQn input goes low when low-level detection is set
(IRQnSCB = IRQnSCA = 0)
• When a falling edge occurs in IRQn input while falling edge detection is
set (IRQnSCB = 0, IRQnSCA = 1)
• When a rising edge occurs in IRQn input while rising edge detection is
set (IRQnSCB = 1, IRQnSCA = 0)
• When a falling or rising edge occurs in IRQn input while both-edge
detection is set (IRQnSCB = IRQnSCA = 1)
(n = 5 to 0)
Note: * Only 0 can be written, to clear the flag.
Page 1322 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010