HD64F2638F20J Datasheet, PDF (445/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 10 16-Bit Timer Pulse Unit (TPU)
Contention between Buffer Register Write and Input Capture: If the input capture signal is
generated in the T₂ state of a buffer write cycle, the buffer operation takes precedence and the
write to the buffer register is not performed.
Figure 10-55 shows the timing in this case.
Buffer register write cycle
T₁
T₂
φ
Address
Write signal
Input capture
signal
TCNT
Buffer register
address
N
TGR
M
N
Buffer
M
register
Figure 10-55 Contention between Buffer Register Write and Input Capture
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 395 of 1458