HD64F2638F20J Datasheet, PDF (303/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 9 I/O Ports
9.6.2 Register Configuration
Table 9-8 shows the port A register configuration.
Table 9-8 Port A Registers
Name
Abbreviation
Port A data direction register
PADDR
Port A data register
PADR
Port A register
PORTA
Port A MOS pull-up control register PAPCR
Port A open-drain control register PAODR
Notes: 1. Lower 16 bits of the address.
2. Value of bits 3 to 0.
R/W
W
R/W
R
R/W
R/W
Initial Value^*2
H'0
H'0
Undefined
H'0
H'0
Address^*1
H'FE39
H'FF09
H'FFB9
H'FF40
H'FF47
Port A Data Direction Register (PADDR)
Bit
:
7
6
5
4
3
2
1
0
—
—
—
— PA3DDR PA2DDR PA1DDR PA0DDR
Initial value : Undefined Undefined Undefined Undefined 0
0
0
0
R/W
:—
—
—
—
W
W
W
W
PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port A. PADDR cannot be read; if it is, an undefined value will be read.
Bits 7 to 4 are reserved; they return an undetermined value if read.
PADDR is initialized to H'0 (bits 3 to 0) by a reset, and in hardware standby mode. It retains its
prior state in software standby mode. The OPE bit in SBYCR is used to select whether the address
output pins retain their output state or become high-impedance when a transition is made to
software standby mode.
• Modes 4 to 6
The corresponding port A pins become address outputs in accordance with the setting of bits
AE3 to AE0 in PFCR, irrespective of the value of bits PA3DDR to PA0DDR. When pins are
not used as address outputs, setting a PADDR bit to 1 makes the corresponding port A pin an
output port, while clearing the bit to 0 makes the pin an input port.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 253 of 1458