HD64F2638F20J Datasheet, PDF (76/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 2 CPU
• High-speed operation
⎯ All frequently-used instructions execute in one or two states
⎯ Maximum clock rate
: 20 MHz
⎯ 8/16/32-bit register-register add/subtract : 50 ns
⎯ 8 × 8-bit register-register multiply
: 150 ns
⎯ 16 ÷ 8-bit register-register divide
: 600 ns
⎯ 16 × 16-bit register-register multiply : 200 ns
⎯ 32 ÷ 16-bit register-register divide
: 1000 ns
• Two CPU operating modes
⎯ Normal mode*
⎯ Advanced mode
Note: * Not available in the chip.
• Power-down state
⎯ Transition to power-down state by SLEEP instruction
⎯ CPU clock speed selection
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU
The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.
• Register configuration
The MAC register is supported only by the H8S/2600 CPU.
• Basic instructions
The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the
H8S/2600 CPU.
• Number of execution states
The number of execution states of the MULXU and MULXS instructions is different in each
CPU.
Execution States
Instruction
Mnemonic
H8S/2600
H8S/2000
MULXU
MULXU.B Rs, Rd
3
12
MULXU.W Rs, ERd 4
20
MULXS
MULXS.B Rs, Rd
4
13
MULXS.W Rs, ERd
5
21
Page 26 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010