HD64F2638F20J Datasheet, PDF (30/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

2.8.3 Exception-Handling State .................................................................................... 65
2.8.4 Program Execution State ..................................................................................... 68
2.8.5 Bus-Released State .............................................................................................. 68
2.8.6 Power-Down State ............................................................................................... 68
2.9 Basic Timing..................................................................................................................... 69
2.9.1 Overview ............................................................................................................. 69
2.9.2 On-Chip Memory (ROM, RAM) ......................................................................... 69
2.9.3 On-Chip Supporting Module Access Timing ...................................................... 71
2.9.4 On-Chip HCAN Module Access Timing............................................................. 73
2.9.5 Port H and J Register Access Timing .................................................................. 75
2.9.6 External Address Space Access Timing .............................................................. 76
2.10 Usage Note........................................................................................................................ 77
2.10.1 TAS Instruction ................................................................................................... 77
2.10.2 STM/LDM Instructions ....................................................................................... 77
2.10.3 Caution to Observe when Using Bit Manipulation Instructions .......................... 77
Section 3 MCU Operating Modes .................................................................................. 79
3.1 Overview........................................................................................................................... 79
3.1.1 Operating Mode Selection ................................................................................... 79
3.1.2 Register Configuration......................................................................................... 80
3.2 Register Descriptions ........................................................................................................ 80
3.2.1 Mode Control Register (MDCR) ......................................................................... 80
3.2.2 System Control Register (SYSCR) ...................................................................... 81
3.2.3 Pin Function Control Register (PFCR) ................................................................ 83
3.3 Operating Mode Descriptions ........................................................................................... 85
3.3.1 Mode 4................................................................................................................. 85
3.3.2 Mode 5................................................................................................................. 85
3.3.3 Mode 6................................................................................................................. 85
3.3.4 Mode 7................................................................................................................. 86
3.4 Pin Functions in Each Operating Mode ............................................................................ 86
3.5 Address Map in Each Operating Mode............................................................................. 87
Section 4 Exception Handling ......................................................................................... 93
4.1 Overview........................................................................................................................... 93
4.1.1 Exception Handling Types and Priority............................................................... 93
4.1.2 Exception Handling Operation ............................................................................ 94
4.1.3 Exception Vector Table ....................................................................................... 94
4.2 Reset ................................................................................................................................. 96
4.2.1 Overview ............................................................................................................. 96
4.2.2 Reset Sequence .................................................................................................... 96
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REJ09B0103-0800 Rev. 8.00
May 28, 2010