HD64F2638F20J Datasheet, PDF (633/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 15 I²C Bus Interface [Option]
(Only for the H8S/2638, H8S/2639, and H8S/2630)
Master receive mode
Set TRS = 0 (ICCR)
Set ACKB = 0 (ICSR)
Clear IRIC flag in ICCR
Set WAIT = 1 (ICMR)
Read ICDR
[1] Set to receive mode
[2] Receive start, dummy read
Read IRIC flag in ICCR
No
IRIC = 1?
Yes
No
IRTR = 1?
Yes
Final receive?
Yes
No
Read ICDR
Clear IRIC flag in ICCR
[3] Receive wait state (IRIC set at falling edge of 8th clock cycle)
or
Wait for end of reception of 1 byte (IRIC set at rising edge
of 9th clock cycle)
[4] Data receive completed judgment
[5] Read receive data
[6] Clear IRIC flag (cancel wait state)
Set ACKB = 1 (ICSR)
1 clock cycle wait state
Set TRS = 1 (ICCR)
Read ICDR
Clear IRIC flag in ICCR
[7] Set acknowledge data for final receive
[8] Wait time until TRS setting
[9] Set TRS to generate stop condition
[10] Read receive data
[11] Clear IRIC flag (cancel wait state)
Read IRIC flag in ICCR
No
IRIC = 1?
Yes
IRTR = 1?
Yes
No
Clear IRIC flag in ICCR
[12] Receive wait state (IRIC set at falling edge of 8th clock cycle)
or
Wait for end of reception of 1 byte (IRIC set at rising edge
of 9th clock cycle)
[13] Data receive completed judgment
[14] Clear IRIC flag (cancel wait state)
Set WAIT = 0 (ICMR)
Clear IRIC flag in ICCR
Read ICDR
Write BBSY = 0
and SCP = 0 (ICCR)
End
[15] Cancel wait mode
Clear IRIC flag (IRIC flag should be cleared when WAIT = 0)
[16] Read final receive data
[17] Generate stop condition
Figure 15-10 Flowchart for Master Receive Mode (Receiving Multiple Bytes) (WAIT = 1)
(Example)
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 583 of 1458