HD64F2638F20J Datasheet, PDF (187/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 6 PC Break Controller (PBC)
Section 6 PC Break Controller (PBC)
Note: The H8S/2635 Group is not equipped with a PBC.
6.1 Overview
The PC break controller (PBC) provides functions that simplify program debugging. Using these
functions, it is easy to create a self-monitoring debugger, enabling programs to be debugged with
the chip alone, without using an in-circuit emulator. Four break conditions can be set in the PBC:
instruction fetch, data read, data write, and data read/write.
6.1.1 Features
The PC break controller has the following features:
• Two break channels (A and B)
• The following can be set as break compare conditions:
⎯ 24 address bits
Bit masking possible
⎯ Bus cycle
Instruction fetch
Data access: data read, data write, data read/write
⎯ Bus master
Either CPU or CPU/DTC can be selected
• The timing of PC break exception handling after the occurrence of a break condition is as
follows:
⎯ Immediately before execution of the instruction fetched at the set address (instruction
fetch)
⎯ Immediately after execution of the instruction that accesses data at the set address (data
access)
• Module stop mode can be set
⎯ The initial setting is for PBC operation to be halted. Register access is enabled by clearing
module stop mode.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 137 of 1458