HD64F2638F20J Datasheet, PDF (1428/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Appendix B Internal I/O Register
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
TCR2—Timer Control Register 2
H'FF30
TPU2
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
⎯ CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
0
0
0
0
0
0
0
0
⎯
R/W R/W R/W R/W R/W R/W R/W
Time Prescaler
0 0 0 Internal clock: counts on φ/1
1 Internal clock: counts on φ/4
1 0 Internal clock: counts on φ/16
1 Internal clock: counts on φ/64
1 0 0 External clock: counts on TCLKA pin input
1 External clock: counts on TCLKB pin input
1 0 External clock: counts on TCLKC pin input
1 Internal clock: counts on φ/1024
Note: This setting is ignored when channel 2 is in phase
counting mode.
Clock Edge
0 0 Count at rising edge
1 Count at falling edge
1 ⎯ Count at both edges
Note: This setting is ignored when channel 2 is in phase
counting mode.
Internal clock edge selection is valid when the input
clock is φ/4 or slower. This setting is ignored if the
input clock is φ/1, or when overflow/underflow of
another channel is selected.
Counter Clear
0 0 TCNT clearing disabled
1 TCNT cleared by TGRA compare match/input capture
1 0 TCNT cleared by TGRB compare match/input capture
1 TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation*
Note: * Synchronous operation setting is performed by setting the
SYNC bit in TSYR to 1.
Page 1378 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010