HD64F2638F20J Datasheet, PDF (1180/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Appendix A Instruction Set
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
A.6 Condition Code Modification
This section indicates the effect of each CPU instruction on the condition code. The notation used
in the table is defined below.
m = 31 for longword operands
15 for word operands
7 for byte operands
Si
The i-th bit of the source operand
Di
The i-th bit of the destination operand
Ri
The i-th bit of the result
Dn The specified bit in the destination operand
—
Not affected
Modified according to the result of the instruction (see definition)
0
Always cleared to 0
1
Always set to 1
*
Undetermined (no guaranteed value)
Z'
Z flag before instruction execution
C'
C flag before instruction execution
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REJ09B0103-0800 Rev. 8.00
May 28, 2010