HD64F2638F20J Datasheet, PDF (126/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 2 CPU
φ
Address bus
AS
RD
HWR, LWR
Data bus
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Bus cycle
T₁
T₂
T₃
T₄
Held
High
High
High
High impedance
Figure 2-25 Pin States in Access to Ports H and J Registers and On-Chip Motor Control
PWM Timer Module
2.9.6 External Address Space Access Timing
The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or
three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to
section 7, Bus Controller.
Page 76 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010