HD64F2638F20J Datasheet, PDF (628/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 15 I²C Bus Interface [Option]
(Only for the H8S/2638, H8S/2639, and H8S/2630)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
15.3.2 Initial Setting
At startup the following procedure is used to initialize the IIC.
Start initialization
Set MSTP4 = 0 (IIC0)
MSTP3 = 0 (IIC1)
(MSTPCRB)
Set IICE = 1 (SCRX)
Set ICE = 0 (ICCR)
Clear module stop
Enable CPU access by IIC control register and data register
Enable SAR and SARX access
Set SAR and SARX
Set ICE = 1 (ICCR)
Set ICSR
Set transfer format for 1st slave address, 2nd slave address,
and IIC (SVA8−SVA0, FS, SVAX6−SVAX0, FSX)
Enable IMCR and IMDR access. Use SCL and SDA pins is IIC
port
Set acknowledge bit (ACKB)
Set SCRX
Set transfer rate (IICX)
Set IMCR
Set ICCR
Set transfer format, wait insertion, and transfer rate (MLS,
WAIT, CKS2−CKS0)
Set interrupt enable, transfer mode, and acknowledge
judgment (IEIC, MST, TRS, ACKE)
Transmit/receive start
Figure 15-6 Flowchart for IIC Initialization (Example)
Note:
The ICMR register should be written to only after transmit or receive operations have
completed.
Writing to the ICMR register while a transmit or receive operation is in progress could
cause an erroneous value to be written to bit counter bits BC2 to BC0. This could result in
improper operation.
15.3.3 Master Transmit Operation
In I²C bus format master transmit mode, the master device outputs the transmit clock and transmit
data, and the slave device returns an acknowledge signal.
Figure 15-7 is a flowchart showing an example of the master transmit mode.
Page 578 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010