HD64F2638F20J Datasheet, PDF (170/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 5 Interrupt Controller
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Interrupt Source
Origin of
Vector
Address^*1
Interrupt Vector Advanced
Source Number Mode
IPR
Priority
PWM1
PWM
104
channel 1
H'01A0
IPRM6 to 4 High
PWM2
ERS0, OVR0, RM1, SLE0,
RM0
PWM
105
channel 2
HCAN1^*3 106
107
H'01A4
H'01A8
H'01AC
ERS0, OVR0, RM1, SLE0,
RM0
HCAN0 108
109
H'01B0
H'01B4
IPRM2 to 0
Reserved for system use
—
110
H'01B8
111
H'01BC
Low
Notes: 1. Lower 16 bits of the start address.
2. I²C is available as an option in the H8S/2638, H8S/2639, and H8S/2630 only. The
product equipped with the I²C bus interface is the W-mask version.
3. The DTC, PC break, and HCAN1 interrupts are reserved in the H8S/2635 Group.
5.4 Interrupt Operation
5.4.1 Interrupt Control Modes and Interrupt Operation
Interrupt operations in the chip differ depending on the interrupt control mode.
NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In
the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for
each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request. Interrupt
sources for which the enable bits are set to 1 are controlled by the interrupt controller.
Table 5-5 shows the interrupt control modes.
The interrupt controller performs interrupt control according to the interrupt control mode set by
the INTM1 and INTM0 bits in SYSCR, the priorities set in IPR, and the masking state indicated
by the I bit in the CPU’s CCR, and bits I2 to I0 in EXR.
Page 120 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010