HD64F2638F20J Datasheet, PDF (623/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 15 I²C Bus Interface [Option]
(Only for the H8S/2638, H8S/2639, and H8S/2630)
15.2.7 Serial Control Register X (SCRX)
Bit
:7
6
5
4
3
2
1
0
⎯
IICX1 IICX0 IICE
⎯
⎯
⎯
⎯
Initial value : 0
0
0
0
1
0
0
0
R/W
: R/W
R/W
R/W
R/W
R
R/W R/W R/W
SCRX is an 8-bit readable/writable register that controls register access, the I²C interface
operating mode. If a module controlled by SCRX is not used, do not write 1 to the corresponding
bit.
SCRX is initialized to H'08 by a reset and in hardware standby mode.
Bit 7—Reserved: Do not set 1.
Bit 6—I²C Transfer Select 1 (IICX1): This bit, together with bits CKS2 to CKS0 in ICMR of
IIC1, selects the transfer rate in master mode. For details, see section 15.2.4, I²C Bus Mode
Register (ICMR).
Bit 5—I²C Transfer Select 0 (IICX0): This bit, together with bits CKS2 to CKS0 in ICMR of
IIC0, selects the transfer rate in master mode. For details, see section 15.2.4, I²C Bus Mode
Register (ICMR).
Bit 4—I²C Master Enable (IICE): Controls CPU access to the I²C bus interface data and control
registers (ICCR, ICSR, ICDR/SARX, ICMR/SAR).
Bit 4
IICE
0
1
Description
CPU access to I²C bus interface data and control registers is disabled
CPU access to I²C bus interface data and control registers is enabled
(Initial value)
Bit 3— Reserved: Always returns a value of 1 if it is read.
Bits 2 to 0—Reserved: Do not set 1.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 573 of 1458