HD64F2638F20J Datasheet, PDF (192/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 6 PC Break Controller (PBC)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Bits 2 and 1—Break Condition Select A (CSELA1, CSELA0): These bits selection an
instruction fetch, data read, data write, or data read/write cycle as the channel A break condition.
Bit 2
CSELA1
0
1
Bit 1
CSELA0
0
1
0
1
Description
Instruction fetch is used as break condition
Data read cycle is used as break condition
Data write cycle is used as break condition
Data read/write cycle is used as break condition
(Initial value)
Bit 0—Break Interrupt Enable A (BIEA): Enables or disables channel A PC break interrupts.
Bit 0
BIEA
0
1
Description
PC break interrupts are disabled
PC break interrupts are enabled
(Initial value)
6.2.4 Break Control Register B (BCRB)
BCRB is the channel B break control register. The bit configuration is the same as for BCRA.
6.2.5 Module Stop Control Register C (MSTPCRC)
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MSTPCRC is an 8-bit readable/writable register that performs module stop mode control.
When the MSTPC4 bit is set to 1, PC break controller operation is stopped at the end of the bus
cycle, and module stop mode is entered. Register read/write accesses are not possible in module
stop mode. For details, see section 23A.5, 23B.5, Module Stop Mode.
MSTPCRC is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 4—Module Stop (MSTPC4): Specifies the PC break controller module stop mode.
Page 142 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010