HD64F2638F20J Datasheet, PDF (476/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 12 Watchdog Timer
12.1.2 Block Diagram
Figures 12-1 (a) and 12-1 (b) show block diagrams of the WDT.
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
WOVI 0
(interrupt request
signal)
Internal reset signal^*1
Interrupt
control
Reset
control
Overflow
Clock
Clock
select
φ/2^*2
φ/64^*2
φ/128^*2
φ/512^*2
φ/2048^*2
φ/8192^*2
φ/32768^*2
φ/131072^*2
Internal clock
sources
RSTCSR
TCNT
TSCR
Module bus
Bus
interface
WDT
Legend:
TCSR: Timer control/status register
TCNT: Timer counter
RSTCSR: Reset control/status register
Notes: 1. The type of internal reset signal depends on a register setting.
2. In the U-mask and W-mask versions, and H8S/2635 Group, φ in subactive and subsleep modes
operates as φSUB.
Figure 12-1 (a) Block Diagram of WDT0
Page 426 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010