HD64F2638F20J Datasheet, PDF (828/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 21A ROM
(H8S/2636 Group)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
21A.9.3 Erase Mode
When erasing flash memory, the single-block erase flowchart shown in figure 21A-13 should be
followed.
The wait times after bits are set or cleared in the flash memory control register 1 (FLMCR1) and
the maximum number of erase operations (N) are shown in section 24.1.7, Flash Memory
Characteristics.
To erase flash memory contents, make a 1-bit setting for the flash memory area to be erased in
erase block register 1 and 2 (EBR1, EBR2) at least (t_sswe) µs after setting the SWE bit to 1 in
FLMCR1. Next, the watchdog timer (WDT) is set to prevent overerasing due to program runaway,
etc. Set a value of about 19.8 ms as the WDT overflow period. Preparation for entering erase mode
(erase setup) is performed next by setting the ESU bit in FLMCR1. The operating mode is then
switched to erase mode by setting the E bit in FLMCR1 after the elapse of at least (t_sesu) µs. The
time during which the E bit is set is the flash memory erase time. Ensure that the erase time does
not exceed (t_se) ms.
Note: With flash memory erasing, preprogramming (setting all memory data in the memory to
be erased to all 0) is not necessary before starting the erase procedure.
Page 778 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010