HD64F2638F20J Datasheet, PDF (1210/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Appendix B Internal I/O Register
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
MRB—DTC Mode Register B
H'EBC0 to H'EFBF
DTC^*
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
CHNE DISEL ⎯
⎯
⎯
⎯
⎯
⎯
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
DTC Interrupt Select
0 After a data transfer ends, the CPU interrupt is
disabled unless the transfer counter is 0
1 After a data transfer ends, the CPU interrupt is
enabled
DTC Chain Transfer Enable
0 End of DTC data transfer
1 DTC chain transfer
Note: * This register is not available in the H8S/2635 Group.
SAR—DTC Source Address Register
H'EBC0 to H'EFBF
DTC^*
Bit
23 22 21 20 19
---
43210
---
Initial value Unde- Unde- Unde- Unde- Unde-
---
Unde- Unde- Unde- Unde- Unde-
fined fined fined fined fined
fined fined fined fined fined
---
Read/Write ⎯ ⎯ ⎯ ⎯ ⎯
⎯⎯⎯⎯⎯
Specify DTC transfer data source address
Note: * This register is not available in the H8S/2635 Group.
DAR—DTC Destination Address Register
H'EBC0 to H'EFBF
DTC^*
Bit
23 22 21 20 19
---
43210
---
Initial value Unde- Unde- Unde- Unde- Unde-
---
Unde- Unde- Unde- Unde- Unde-
fined fined fined fined fined
fined fined fined fined fined
---
Read/Write ⎯ ⎯ ⎯ ⎯ ⎯
⎯⎯⎯⎯⎯
Specify DTC transfer data destination address
Note: * This register is not available in the H8S/2635 Group.
Page 1160 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010