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HD64F2638F20J Datasheet, PDF (937/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 21C ROM
(H8S/2635 Group)
21C.10 Protection
There are three kinds of flash memory program/erase protection: hardware protection, software
protection, and error protection.
21C.10.1 Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly
disabled or aborted. Hardware protection is reset by settings in flash memory control register 1
(FLMCR1), flash memory control register 2 (FLMCR2), erase block register 1 (EBR1), and erase
block register 2 (EBR2). The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained in the
error-protected state (See table 21C-11).
Table 21C-11 Hardware Protection
Item
FWE pin protection
Reset/standby
protection
Functions
Description
Program Erase
• When a low level is input to the FWE pin, Yes
Yes
FLMCR1, FLMCR2, (except bit FLER) EBR1,
and EBR2 are initialized, and the
program/erase-protected state is entered.
• In a reset (including a WDT reset) and in Yes
Yes
standby mode, FLMCR1, FLMCR2, EBR1,
and EBR2 are initialized, and the
program/erase-protected state is entered.
• In a reset via the RES pin, the reset state is
not entered unless the RES pin is held low
until oscillation stabilizes after powering on.
In the case of a reset during operation, hold
the RES pin low for the RES pulse width
specified in the AC Characteristics section.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 887 of 1458