HD64F2638F20J Datasheet, PDF (245/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
8.2.3
Bit
DTC Source Address Register (SAR)
: 23 22 21 20 19
Initial value:
R/W
:
*****
⎯⎯⎯⎯⎯
Section 8 Data Transfer Controller (DTC)
43210
*****
⎯⎯⎯⎯⎯
*: Undefined
SAR is a 24-bit register that designates the source address of data to be transferred by the DTC.
For word-size transfer, specify an even source address.
8.2.4 DTC Destination Address Register (DAR)
Bit
: 23 22 21 20 19
43210
Initial value :
R/W
:
*****
⎯⎯⎯⎯⎯
*****
⎯⎯⎯⎯⎯
*: Undefined
DAR is a 24-bit register that designates the destination address of data to be transferred by the
DTC. For word-size transfer, specify an even destination address.
8.2.5
Bit
DTC Transfer Count Register A (CRA)
: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value:
R/W
:
****************
⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
CRAH
CRAL
*: Undefined
CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 195 of 1458