HD64F2638F20J Datasheet, PDF (366/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the input clock edge.
When the input clock is counted using both edges, the input clock period is halved (e.g. φ/4 both
edges = φ/2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is
ignored and the phase counting mode setting has priority.
Bit 4
CKEG1
Bit 3
CKEG0
Description
0
0
Count at rising edge
(Initial value)
1
Count at falling edge
1
—
Count at both edges
Note: Internal clock edge selection is valid when the input clock is φ/4 or slower. This setting is
ignored if the input clock is φ/1, or when overflow/underflow of another channel is selected.
Bits 2 to 0—Time Prescaler 2, 1, and 0 (TPSC2 to TPSC0): These bits select the TCNT counter
clock. The clock source can be selected independently for each channel. Table 10-4 shows the
clock sources that can be set for each channel.
Table 10-4 TPU Clock Sources
Channel
φ/1
0
Internal Clock
External Clock
Overflow/
Underflow
φ/4 φ/16 φ/64 φ/256 φ/1024 φ/4096 TCLKA TCLKB TCLKC TCLKD on Another
Channel
1
2
3
4
5
Legend:
: Setting
Blank: No setting
Page 316 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010