HD64F2638F20J Datasheet, PDF (829/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 21A ROM
(H8S/2636 Group)
21A.9.4 Erase-Verify Mode
In erase-verify mode, data is read after memory has been erased to check whether it has been
correctly erased.
After the elapse of the fixed erase time, clear the E bit in FLMCR1, then wait for at least (t_ce) µs
before clearing the ESU bit to exit erase mode. After exiting erase mode, the watchdog timer
setting is also cleared. The operating mode is then switched to erase-verify mode by setting the EV
bit in FLMCR1. Before reading in erase-verify mode, a dummy write of H'FF data should be made
to the addresses to be read. The dummy write should be executed after the elapse of (t_sev) µs or
more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at
the latched address is read. Wait at least (t_sevr) µs after the dummy write before performing this
read operation. If the read data has been erased (all 1), a dummy write is performed to the next
address, and erase-verify is performed. If the read data is unerased, set erase mode again, and
repeat the erase/erase-verify sequence as before. The maximum number of repetitions of the
erase/erase-verify sequence is indicated by the maximum erase count (N). When verification is
completed, exit erase-verify mode, and wait for at least (t_cev) µs. If erasure has been completed on
all the erase blocks, clear the SWE bit in FLMCR1, and leave a wait time of at least (t_cswe) µs.
If erasing multiple blocks, set a single bit in EBR1/EBR2 for the next block to be erased, and
repeat the erase/erase-verify sequence as before.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 779 of 1458