HD64F2638F20J Datasheet, PDF (605/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 15 I²C Bus Interface [Option]
(Only for the H8S/2638, H8S/2639, and H8S/2630)
Bit 0—Format Select X (FSX): Used together with the FS bit in SAR to select the
communication format.
• I²C bus format: addressing format with acknowledge bit
• Synchronous serial format: non-addressing format without acknowledge bit, for master mode
only
The FSX bit also specifies whether or not SARX slave address recognition is performed in slave
mode. For details, see the description of the FS bit in SAR.
15.2.4 I²C Bus Mode Register (ICMR)
Bit
:7
6
5
4
3
2
1
0
MLS WAIT CKS2 CKS1 CKS0 BC2 BC1 BC0
Initial value : 0
0
0
0
0
0
0
0
R/W
: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred
first, performs master mode wait control, and selects the master mode transfer clock frequency and
the transfer bit count. ICMR is assigned to the same address as SAR. ICMR can be written and
read only when the ICE bit is set to 1 in ICCR.
ICMR is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—MSB-First/LSB-First Select (MLS): Selects whether data is transferred MSB-first or
LSB-first.
If the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and
receive data are stored differently. Transmit data should be written justified toward the MSB side
when MLS = 0, and toward the LSB side when MLS = 1. Receive data bits read from the LSB
side should be treated as valid when MLS = 0, and bits read from the MSB side when MLS = 1.
Do not set this bit to 1 when the I²C bus format is used.
Bit 7
MLS
0
1
Description
MSB-first
LSB-first
(Initial value)
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 555 of 1458