HD64F2638F20J Datasheet, PDF (155/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 5 Interrupt Controller
Section 5 Interrupt Controller
5.1 Overview
5.1.1 Features
The chip controls interrupts by means of an interrupt controller. The interrupt controller has the
following features:
• Two interrupt control modes
⎯ Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in
the system control register (SYSCR).
• Priorities settable with IPR
⎯ An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority
levels can be set for each module for all interrupts except NMI.
⎯ NMI is assigned the highest priority level of 8, and can be accepted at all times.
• Independent vector addresses
⎯ All interrupt sources are assigned independent vector addresses, making it unnecessary for
the source to be identified in the interrupt handling routine.
• Seven external interrupts
⎯ NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling
edge can be selected for NMI.
⎯ Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQ5
to IRQ0.
• DTC control*
⎯ DTC activation is performed by means of interrupts.
Note: * The H8S/2635 Group is not equipped with a DTC.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 105 of 1458