HD64F2638F20J Datasheet, PDF (776/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 19 Motor Control PWM Timer
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
PWCNT1
(lower 10 bits)
0
1
PWCYR1
(lower 10 bits)
N
PWDTR1
(lower 10 bits)
M
PWM output
(M = 0)
PWM output
(0 < M < N)
PWM output
(N ≤ M)
N−2 N−1 0
Figure 19-5 Differences in PWM Output According to Duty Register Set Value
(OPS = 0 in PWPR1)
19.2.7 PWM Buffer Registers 1A, 1C, 1E, 1G (PWBFR1A, 1C, 1E, 1G)
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
— — — OTS — — DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0
Initial value 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0
Read/Write — — — R/W — — R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
There are four 16-bit read/write PWBFR1 registers (PWBFR1A, 1C, 1E, 1G). When a PWCYR1
compare match occurs, data is transferred from PWBFR1A to PWDTR1A, from PWBFR1C to
PWDTR1C, from PWBFR1E to PWDTR1E, and from PWBFR1G to PWDTR1G.
PWBFR1 is initialized to H'EC00 upon reset, and in standby mode, watch mode*, subactive
mode*, subsleep mode*, and module stop mode.
Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the
U-mask and W-mask versions, and H8S/2635 Group only.
These functions cannot be used with the other versions.
Page 726 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010