HD64F2638F20J Datasheet, PDF (1209/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Appendix B Internal I/O Register
MRA—DTC Mode Register A
H'EBC0 to H'EFBF
DTC^*
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
SM1 SM0 DM1 DM0 MD1 MD0 DTS
Sz
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
DTC Data Transfer Size
0 Byte-size transfer
1 Word-size transfer
DTC Transfer Mode Select
0 Destination side is repeat
area or block area
1 Source side is repeat area
or block area
DTC Mode
0 0 Normal mode
1 Repeat mode
1 0 Block transfer mode
1⎯
Destination Address Mode
0 ⎯ DAR is fixed
1 0 DAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
1 DAR is decremented after a transfer
(by −1 when Sz = 0; by −2 when Sz = 1)
Source Address Mode
0 ⎯ SAR is fixed
1 0 SAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
1 SAR is decremented after a transfer
(by −1 when Sz = 0; by −2 when Sz = 1)
Note: * This register is not available in the H8S/2635 Group.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 1159 of 1458