HD64F2638F20J Datasheet, PDF (1093/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 24 Electrical Characteristics
Condition
Item
Symbol Min. Max. Unit Test Conditions
HCAN^* Transmit data delay time
tHTXD
—
100
ns
Figure 24-27
Receive data setup time
tHRXS
100
—
Receive data hold time
tHRXH
100
—
Note: * The HCAN input signal is asynchronous. However, its state is judged to have changed at
the leading edge (two clock cycles) of the CK clock signal shown in figure 24-27. The HCAN
output signal is also asynchronous. Its state changes based on the leading edge (two clock
cycles) of the CK clock signal shown in figure 24-27.
Table 24-43 I²C Bus Timing [Option]*¹
Conditions: V_CC = 4.5 V to 5.5 V, PWMV_CC = 4.5 V to 5.5 V, AV_CC = 4.5 V to 5.5 V,
V_ref = 4.5 V to AV_CC, V_SS = PWMV_SS = PLLV_SS = AV_SS = 0 V,
φ = 5 MHz to maximum operating frequency, T_a = –20°C to +75°C
(regular specifications), T_a = –40°C to +85°C (wide-range specifications)
Condition
Item
Symbol Min. Typ. Max. Unit Notes
SCL input cycle time
SCL input high pulse width
SCL input low pulse width
SCL, SDA input rise time
SCL, SDA input fall time
SCL, SDA input spike pulse
elimination time
tSCL
tSCLH
tSCLL
tSr
tSf
tSP
12 tcyc —
3 tcyc
—
5 tcyc
—
—
—
—
—
—
—
—
ns
—
ns
—
ns
7.5 tcyc^{*2 ns}
300
ns
1 tcyc
ns
Figure 24-28
SDA input bus free time
tBUF
5 tcyc
—
—
ns
Start condition input hold time
tSTAH
3 tcyc
—
—
ns
Retransmission start condition
tSTAS
3 tcyc
—
—
ns
input setup time
Stop condition input setup time
tSTOS
3 tcyc
—
—
ns
Data input setup time
tSDAS
0.5 tcyc —
—
ns
Data input hold time
tSDAH
0
—
—
ns
SCL, SDA capacitive load
Cb
—
—
400
pF
Notes: 1. Available when using I²C bus interface (the W-mask version only).
2. 17.5 tcyc can be set according to the clock selected for use by the I²C module. For
details, see section 15.4, Usage Notes.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 1043 of 1458