HD64F2638F20J Datasheet, PDF (654/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 15 I²C Bus Interface [Option]
(Only for the H8S/2638, H8S/2639, and H8S/2630)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
• Notes on Start Condition Issuance for Retransmission
Figure 15-22 shows the timing of start condition issuance for retransmission, and the timing
for subsequently writing data to ICDR, together with the corresponding flowchart.
IRIC = 1 ?
No
Yes
Clear IRIC in ICSR
Start condition
No
issuance?
Yes
Read SCL pin
SCL = Low ?
No
[1]
Other processing
[2]
[1] Wait for end of 1-byte transfer
[2] Determine whether SCL is low
[3] Issue restart condition instruction for retransmission
[4] Determine whether SCL is high
[5] Set transmit data (slave address + R/W)
Note: Program so that processing from [3] to [5] is
executed continuously.
Yes
Write BBSY = 1,
SCP = 0 (ICSR)
[3]
Read SCL pin
SCL = High ?
No
[4]
Yes
Write transmit data to ICDR
[5]
SCL
SDA
ACK
IRIC
Start condition
(retransmission)
Bit 7
[1] IRIC determination [2] Determination
of SCL = low
[4] Determination
of SCL = high
[3] Start condition
instruction issuance
[5] ICDR write
Figure 15-22 Flowchart and Timing of Start Condition Instruction Issuance for
Retransmission
Page 604 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010