HD64F2638F20J Datasheet, PDF (144/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 4 Exception Handling
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
4.1.2 Exception Handling Operation
Exceptions originate from various sources. Trap instructions and interrupts are handled as follows:
1. The program counter (PC), condition code register (CCR), and extended register (EXR) are
pushed onto the stack.
2. The interrupt mask bits are updated. The T bit is cleared to 0.
3. A vector address corresponding to the exception source is generated, and program execution
starts from that address.
For a reset exception, steps 2 and 3 above are carried out.
4.1.3 Exception Vector Table
The exception sources are classified as shown in figure 4-1. Different vector addresses are
assigned to different exception sources.
Table 4-2 lists the exception sources and their vector addresses.
Reset
Exception
sources
Trace
Interrupts
External interrupts: NMI, IRQ5 to IRQ0
Internal interrupts: 49 (+3: Option) interrupt sources in
on-chip supporting modules
Trap instruction
Figure 4-1 Exception Sources
Page 94 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010