HD64F2638F20J Datasheet, PDF (918/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 21C ROM
(H8S/2635 Group)
Table 21C-7 Flash Memory Erase Blocks
Block (Size)
EB0 (4 kbytes)
EB1 (4 kbytes)
EB2 (4 kbytes)
EB3 (4 kbytes)
EB4 (4 kbytes)
EB5 (4 kbytes)
EB6 (4 kbytes)
EB7 (4 kbytes)
EB8 (32 kbytes)
EB9 (64 kbytes)
EB10 (64 kbytes)
Addresses
H'000000 to H'000FFF
H'001000 to H'001FFF
H'002000 to H'002FFF
H'003000 to H'003FFF
H'004000 to H'004FFF
H'005000 to H'005FFF
H'006000 to H'006FFF
H'007000 to H'007FFF
H'008000 to H'00FFFF
H'010000 to H'01FFFF
H'020000 to H'02FFFF
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
21C.7.5 RAM Emulation Register (RAMER)
RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating
real-time flash memory programming. RAMER initialized to H'00 by a reset and in hardware
standby mode. It is not initialized in software standby mode. RAMER settings should be made in
user mode or user program mode.
Flash memory area divisions are shown in table 21C-8. To ensure correct operation of the
emulation function, the ROM for which RAM emulation is performed should not be accessed
immediately after this register has been modified. Normal execution of an access immediately
after register modification is not guaranteed.
Bit: 7
—
Initial value: 0
R/W: R
6
5
4
3
2
1
0
—
—
— RAMS RAM2 RAM1 RAM0
0
0
0
0
0
0
0
R
R/W R/W R/W R/W R/W R/W
Page 868 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010