HD64F2638F20J Datasheet, PDF (447/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 10 16-Bit Timer Pulse Unit (TPU)
Contention between TCNT Write and Overflow/Underflow: If there is an up-count or down-
count in the T₂ state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes
precedence and the TCFV/TCFU flag in TSR is not set.
Figure 10-57 shows the operation timing when there is contention between TCNT write and
overflow.
TCNT write cycle
T₁
T₂
φ
Address
TCNT address
Write signal
TCNT
TCFV flag
H'FFFF
Prohibited
TCNT write data
M
Figure 10-57 Contention between TCNT Write and Overflow
Multiplexing of I/O Pins: In the chip, the TCLKA input pin is multiplexed with the TIOCC0 I/O
pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O
pin, and the TCLKD input pin with the TIOCB2 I/O pin. When an external clock is input, compare
match output should not be performed from a multiplexed pin.
Interrupts and Module Stop Mode: If module stop mode is entered when an interrupt has been
requested, it will not be possible to clear the CPU interrupt source or the DTC* activation source.
Interrupts should therefore be disabled before entering module stop mode.
Note: * The DTC is not implemented in the H8S/2635 Group.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 397 of 1458