HD64F2638F20J Datasheet, PDF (8/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Item
Page
2.6.3 Table of
50
Instructions Classified
by Function
Table 2-3 Instructions
Classified by Function
2.8.1 Overview
63
Figure 2-14
Processing States
2.8.3 Exception-
65
Handling State
3.4 Pin Functions in 86
Each Operating Mode
Table 3-3 Pin
Functions in Each
Mode
4.1.1 Exception
93
Handling Types and
Priority
4.2.2 Reset Sequence 97
Figure 4-2 Reset
Sequence (Modes 6
and 7)
Revision (See Manual for Details)
Table amended
Type
Bit-
manipulation
instructions
Instruction
BOR
BIOR
Size*¹
B
B
Function
C ∨ (<bit-No.> of <EAd>) → C
ORs the carry flag with a specified bit in a general
register or memory operand and stores the result in the
carry flag.
C ∨ [ ¬ (<bit-No.> of <EAd>) ] → C
ORs the carry flag with the inverse of a specified bit in a
general register or memory operand and stores the
result in the carry flag.
The bit number is specified by 3-bit immediate data.
Figure amended
Reset state
The CPU and all on-chip supporting modules have been
initialized and are stopped.
Exception-handling
state
A transient state in which the CPU changes the normal
processing flow in response to a reset, trace, interrupt,
or trap instruction.
Description amended
The exception-handling state is a transient state that occurs
when the CPU alters the normal processing flow due to a reset,
trace, interrupt, or trap instruction. The CPU fetches a start
address (vector) from the exception vector table and branches
to that address.
Table amended
Port
Port F
PF7
PF6 to PF4
PF3
Mode 4
P/C*
C
P/C*
Mode 5
P/C*
C
P*/C
Mode 6
P/C*
C
P*/C
Mode 7
P*/C
P
Description amended
As table 4-1 indicates, exception handling may be caused by a
reset, trace, direct transition*, trap instruction, or interrupt.
Exception handling is prioritized as shown in table 4-1.
Figure amended
Vector
fetch
Prefetch of first program
instruction
φ
Page viii of l
REJ09B0103-0800 Rev. 8.00
May 28, 2010