HD64F2638F20J Datasheet, PDF (1426/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Appendix B Internal I/O Register
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
TSR1—Timer Status Register 1
H'FF25
Bit
7
6
5
4
3
2
TCFD
⎯
TCFU TCFV
⎯
⎯
Initial value
1
1
0
0
0
0
Read/Write
R
⎯ R/(W)* R/(W)* ⎯
⎯
TPU1
1
TGFB
0
R/(W)*
0
TGFA
0
R/(W)*
Input Capture/Output Compare Flag A
0 [Clearing conditions]
• When DTC is activated by TGIA interrupt while DISEL bit
of MRB in DTC is 0
• When 0 is written to TGFA after reading TGFA = 1
1 [Setting conditions]
• When TCNT = TGRA while TGRA is functioning as output
compare register
• When TCNT value is transferred to TGRA by input capture
signal while TGRA is functioning as input capture register
Input Capture/Output Compare Flag B
0 [Clearing conditions]
• When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0
• When 0 is written to TGFB after reading TGFB = 1
1 [Setting conditions]
• When TCNT = TGRB while TGRB is functioning as output compare register
• When TCNT value is transferred to TGRB by input capture signal while
TGRB is functioning as input capture register
Overflow Flag
0 [Clearing condition]
• When 0 is written to TCFV after reading TCFV = 1
1 [Setting condition]
• When the TCNT value overflows (changes from H'FFFF to H'0000)
Underflow Flag
0 [Clearing condition]
• When 0 is written to TCFU after reading TCFU = 1
1 [Setting condition]
• When the TCNT value underflows (changes from H'0000 to H'FFFF)
Count Direction Flag
0 TCNT counts down
1 TCNT counts up
Note: * Can only be written with 0 for flag clearing.
Page 1376 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010