HD64F2638F20J Datasheet, PDF (649/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 15 I²C Bus Interface [Option]
(Only for the H8S/2638, H8S/2639, and H8S/2630)
15.4 Usage Notes
• In master mode, if an instruction to generate a start condition is immediately followed by an
instruction to generate a stop condition, neither condition will be output correctly. To output
consecutive start and stop conditions, after issuing the instruction that generates the start
condition, read the relevant ports, check that SCL and SDA are both low, then issue the
instruction that generates the stop condition. Note that SCL may not yet have gone low when
BBSY is cleared to 0.
• Either of the following two conditions will start the next transfer. Pay attention to these
conditions when reading or writing to ICDR.
⎯ Write access to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from
ICDRT to ICDRS)
⎯ Read access to ICDR when ICE = 1 and TRS = 0 (including automatic transfer from
ICDRS to ICDRR)
• Table 15-6 shows the timing of SCL and SDA output in synchronization with the internal
clock. Timings on the bus are determined by the rise and fall times of signals affected by the
bus load capacitance, series resistance, and parallel resistance.
Table 15-6 I²C Bus Timing (SCL and SDA Output)
Item
SCL output cycle time
SCL output high pulse width
SCL output low pulse width
SDA output bus free time
Start condition output hold time
Retransmission start condition output
setup time
Stop condition output setup time
Data output setup time (master)
Data output setup time (slave)
Data output hold time
Symbol
tSCLO
tSCLHO
tSCLLO
tBUFO
tSTAHO
tSTASO
tSTOSO
tSDASO
tSDAHO
Output Timing
28 tcyc to 256 tcyc
0.5 tSCLO
0.5 tSCLO
0.5 tSCLO – 1 tcyc
0.5 tSCLO – 1 tcyc
1 tSCLO
0.5 tSCLO + 2 tcyc
1 tSCLLO – 3 tcyc
1 tSCLL – 3 tcyc
3 tcyc
Unit Notes
ns
Figure 24-28
ns
(reference)
ns
ns
ns
ns
ns
ns
ns
• SCL and SDA input is sampled in synchronization with the internal clock. The AC timing
therefore depends on the system clock cycle t_cyc, as shown in tables 24-19, 24-31, 24-43 in
section 24, Electrical Characteristics. Note that the I²C bus interface AC timing specifications
will not be met with a system clock frequency of less than 5 MHz.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 599 of 1458