HD64F2638F20J Datasheet, PDF (1434/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Appendix B Internal I/O Register
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
TCSR0—Timer Control/Status Register 0
Bit
Initial value
Read/Write
7
OVF
0
R/(W)*
6
WT/IT
0
R/W
5
TME
0
R/W
H'FF74(W), H'FF74(R)
WDT0
4
3
2
1
0
⎯
⎯
CKS2 CKS1 CKS0
1
1
0
0
0
⎯
⎯
R/W
R/W
R/W
Clock Select 2 to 0
CKS2 CKS1 CKS0
Clock
Overflow Period*
(where φ = 20 MHz)
000
φ/2
25.6 μs
1
φ/64
819.2 μs
1
0
φ/128
1.6 ms
1
φ/512
6.6 ms
1
0
0
φ/2048
26.2 ms
1
φ/8192
104.9 ms
1
0
φ/32768
419.4 ms
1
φ/131072
1.68 s
Note: * An overflow period is the time interval between the
start of counting up from H'00 on the TCNT and the
Timer Enable
occurrence of a TCNT overflow.
0 TCNT is initialized to H'00 and halted
1 TCNT counts
Timer Mode Select
0 Interval timer mode: WDT0 requests an interval timer interrupt (WOVI) from
the CPU when the TCNT overflows
1 Watchdog timer mode: A reset is issued when the TCNT overflows if the
RSTE bit of RSTCSR is set to 1*
Note: * For details see section 12.2.3, Reset Control/Status Register (RSTCSR).
Overflow Flag
0 [Clearing conditions]
• Write 0 in the TME bit (Only applies to WDT1)
• Read TCSR* when OVF = 1, then write 0 in OVF
1 _{[Setting condition]}
• When TCNT overflows (changes from H'FF to H'00)
(When internal reset request generation is selected in watchdog timer mode,
OVF is cleared automatically by the internal reset)
Note: * When interval timer interrupts are disabled and OVF is polled,
read the OVF = 1 state at least twice.
Notes: TCSR0 register differs from other registers in being more difficult to write to.
For details see section 12.2.4, Notes on Register Access.
* Only 0 can be written, to clear the flag.
Page 1384 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010