HD64F2638F20J Datasheet, PDF (161/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 5 Interrupt Controller
5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)
ISCRH
Bit
: 15
14
13
12
11
10
9
8
⎯
⎯
⎯
⎯ IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA
Initial value :
0
0
0
0
0
0
0
0
R/W
: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ISCRL
Bit
:
7
6
5
4
3
2
1
0
IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA
Initial value :
0
0
0
0
0
0
0
0
R/W
: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The ISCR registers are 16-bit readable/writable registers that select rising edge, falling edge, or
both edge detection, or level sensing, for the input at pins IRQ5 to IRQ0.
The ISCR registers are initialized to H'0000 by a reset and in hardware standby mode.
Bits 15 to 12—Reserved: These bits are always read as 0, and should only be written with 0.
Bits 11 to 0—IRQ5 Sense Control A and B (IRQ5SCA, IRQ5SCB) to IRQ0 Sense Control A
and B (IRQ0SCA, IRQ0SCB)
Bits 11 to 0
IRQ5SCB to IRQ5SCA to
IRQ0SCB
IRQ0SCA
0
0
1
1
0
1
Description
Interrupt request generated at IRQ5 to IRQ0 input low level
(initial value)
Interrupt request generated at falling edge of IRQ5 to IRQ0 input
Interrupt request generated at rising edge of IRQ5 to IRQ0 input
Interrupt request generated at both falling and rising edges of
IRQ5 to IRQ0 input
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 111 of 1458